1. Field of the Invention
The present invention generally concerns phase locked loops (PLLs), and in particular concerns conditioning circuitry for use with PLLs that employ LC tank voltage-controlled oscillators.
2. Background Information
Phase locked loop (PLL) circuits are used to provide precise control of a frequency output signal in many types of electronic devices. A PLL circuit 10 corresponding to a typical PLL is shown in FIG. 1. PLL circuit 10 employs a closed feedback loop comprising a phase detector 12, a charge pump 14, a loop filter 16, and an oscillator, such as voltage-controlled oscillator (VCO) 18 or a current-controlled oscillator (ICO) (not shown). PLLs may also include a frequency divider 22 in the feedback portion of the loop. Ideally, a PLL will produce an output signal 20 (Fout) having a frequency that matches a reference frequency control signal 24 (Fref).
Phase locked loops work in the following manner. The frequencies of output signal 20 (the loop feedback signal) and frequency control signal 24 are compared by phase detector 12, which outputs a pair of digital control signals 26 and 28 to charge pump 14. It will be understood by those skilled in the art that various types of phase detectors may be used, including phase detectors that output other types of control signals. The control signals selectively activate the current sources in charge pump 14 to control the voltage level of an unfiltered signal 30, which is then filtered by the passive elements (i.e., capacitors C2 and C3 and resister R2) of loop filter 16 to produce a filtered VCO control signal 32. This control signal drives VCO 18, which produces output signal 20, wherein the frequency of output signal 20 is a direct function of the voltage level of filtered VCO control signal 32. In many instances, the frequency characteristic of the various circuit components will be such that it will be preferable to employ frequency divider 22, e.g., when the desired frequency is  greater than 1 MHz.
The characteristics of VCO 18 are very important to the performance of the PLL. Preferably, VCO 18 should be resistant to power supply and ground noise, coupling of spurious frequencies from nearby devices, have minimized jitter, and be able to provide a large variable frequency output based on a small variation in the voltage level of its input control signal.